1. Field of the Invention
This invention relates generally to data processing systems and more particularly to a data processing system having a multilevel memory including at least a first, small, high speed cache memory and one or more large, relatively slower main memories with an integrated control system therefor.
2. Description of the Prior Art
Large data processing systems have processors with substantially increased operating speeds, which has resulted in the need for larger, readily accessible memory systems. In order to fully utilize the increased system operating speeds, it is necessary that the memory or some component thereof, operate at a speed reasonably close to the speed of the processing unit or units. However, it is extremely difficult to reliably randomly access a block of data in a large memory space at high operating speeds in an economical manner.
A solution to the problem is to use a two or more level storage hierarchy including a small, fast cache memory store (hereinafter referred to as a cache) and a large, relatively slower main memory or memories. The system processor unit communicates directly at essentially system speed with the cache. If data requested by the processor unit is not in the cache, it must be found in the main memories and transferred to the cache, where it necessarily replaces an existing block of data.
In order for a cache based system to be effective, there must be a highly efficient control store system to effect data transfer between the main memories and cache and to control any data inputs from the system (channels, processing unit, etc.) to the cache or main memories. If the transfer of data from the main memories is not done efficiently, many of the advantages of using a high speed cache will be lost.
Many of the compromises and trade-offs necessary to optimize a system are not readily apparent. For example, U.S. Pat. No. 3,896,419 describes a cache memory system wherein a data request to the cache store is operated in parallel to the request for data information from the main memory store. A successful retrieval from the cache store aborts the retrieval from the main memory. This would appear to be a very efficient approach, especially where a large number of data requests result in the need to extract data from the main memory. However, with the improved programming techniques which structure systems to require fewer data transfers from the main memory, such an approach can in fact diminish the effective overall operating speed of a system. The reason for this is that even though a successful retrieval from cache aborts the retrieval from main memory, it takes some additional time for the memory to recycle and be ready to handle the next request. Therefore, if a cache "hit" (data in cache) is immediately followed by a cache "miss" (data not in cache) the system performance can be degraded, since the system must wait for the main memory to return to a ready state (to quiesce) before the data acquisition and transfer can begin.
Another disadvantage of such a system is that the various clocks (channel, main memory, cache and processor) must be in sync using the same number of pulse words and the same clock cycles. This, of course, presents design constraints and may result in some inefficiencies in one or more of the subsystems.